Circuit for determining the frequency assigned to a markable instant of a frequency-modulated transmitter

ABSTRACT

A circuit for determining the frequency associated with a markable time point during the frequency-modulated transmission of a transmitter, particularly a wobbulatable transmitter employing an adjustable auxiliary wobble-control voltage determining the frequency in function of time in which the frequency is determined by a counting operation in which the impulses of the transmission are counted for a predetermined period and in which a comparator impulse produced by comparison between a preset voltage and such auxiliary control voltage, which comparator impulse may be utilized directly or indirectly for marking purposes, is utilized to control the admission of impulses of such transmission to the counter for a predetermined period or periods.

FIPMOE' United Sta 411] 3,753,118

N Schlosser Aug. 14, 1973 CIRCUIT FOR DETERMINING THE 3,596,193 7/1971Dunwoodie 331/1711 x FREQUENCY ASSIGNED To A MARKABLE FOREIGN PATENTS 0RAPPLICAnONS INSTANT OF A FREQUENCY'MODULATED 1,080,877 8/1967 GreatBritain 324/78 D TRANSMITTER Karl Schlosser, Planegg, Germany Inventor:Primary ExaminerRobert L. Griffin [7 3] Assignee: SiemensAktiengesellschalt, Berlin, Aimmm 7Tw'u'mT- Eul Germany AnorneyCarltonHill, Donald J. Simpson et al. [22] F1led: July 9, I971 [57] ABSTRACT[21 1 Appl SL014 A circuit for determining the frequency associated witha markable time point during the frequency-modulated [30] ForeignApplication Priority Data transmission of a transmitter, particularly awobbulata- July 22, 1970 Germany P 20 36 449.2 P Y 8 an adjustableauxiliary July 22, 1970 Germany P 20 36 412.9 ble'cmtml "wagedetehhihihB the frequency in function of time in which the frequency isdetermined by a 52 us. c1 325/134, 324/73 D, 325/131 couhhhg Operationin which impulses of the [51] Int. Cl. 1104b 1/02 missim are muted for aPiedetemihed P and 581 Field of Search 325/67, 131, 133, which a empammrimpulse Produced by comparison 325/134; 331/178; 324/78 D, 79 R betweena preset voltage and such auxiliary control voltage, which comparatorimpulse may be utilized di- 56] References Cited rectly or indirectlyfor marking purposes, is utilized to control the admission of impulsesof such transmission UNITED STATES PATENTS to the counter for apredetermined period or periods. 3,379,975 4/1968 Niedereder 325/1313,379,976 4/1968 Niederedeim; 325 131 21 Claims, 6 Drawing FiguresIMPULSE GENERATING CIRCUIT L3 IMPULSE INDICATING COMPARATOR .5 U 7 1COUNTER DEVICE 7 1 r15 rfli Z3 12 1s f' 1e Uv,fx

UNKNOWN FREQ. 2 Us 14 1 15 17 2 MODULATED RECT/ GATE TRANSMISSION 4v CI3 I 25 RCUIT NOBBLE 23k 25 GEN.

I EVAL. 18 v cm.

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IN V EN TOR c2'/"/ cSc/z/asaer BY CIRCUIT FOR DETERMINING THE FREQUENCYASSIGNED TO A MARKABLE INSTANT OF A FREQUENCY-MODULATED TRANSMITTERBACKGROUND OF THE INVENTION The invention is directed to a circuit foruse in determining the frequency associated with a predetermined timepoint during a frequency modulated transmission, the modulatingfrequency of which is variable with a predetermined time functionbetween two limiting values, in particular a wobbulatable transmitteremploying an adjustable auxiliary voltage which is subjected to anamplitude comparison with the wobble voltage, the latter beingrepresentative of the frequency in function of time.

Circuits of this general type heretofore have utilized the comparativeresults, in the form of a comparative impulse, as a marking impulsewhich is supplied to a suitable visual instrument reproducing therecorded frequency curve and appears as a frequency marking indicationon such instrument. While the comparator impulse defines the point oftime, the associated frequency is read on a frequency scale independence upon the position of the frequency marking point on the imagescreen of the visual instrument or by the position of an adjustingdevice for the auxiliary voltage. It will be apparent that in this typeof measurement, reading errors and imprecisions in the frequency scalesemployed cannot be completely avoided.

BRIEF DESCRIPTION OF THE INVENTION The invention, therefore, is directedto the problem of producing a circuit of the type generally referred toin which the frequency pertaining to a markable point of time can bedetermined with higher precision, and in particular without requiringthe pictorial presentation of the frequency mark involved in a visualapparatus In accordance with the invention, this is accomplished byutilizing a comparator impulse formed as a comparative result andadapted to be utilized for a direct or indirect marking of the timepoint, as the means for triggering the production of a gate impulse ofpredetermined, particularly adjustable length, which is adapted to opena gate circuit to an impulse counter whereby the latter may countimpulses of the transmission frequency during such open period.

The invention has the important advantage of enabling a digitalindication that is readily legible and easily recordable in a simplemanner particularly useful in connection with automatic measuringoperations. By suitable selection of the length of the gate impulse, theprecision with which the frequency is determined can be improved ascompared with circuits involving the reading of a frequency markposition. For achieving this improvement, the gate impulse length isselected at a value smaller than the borderline value which justcorresponds with the image screen resolution at the frequency markdisplay in relation to the time required for the traverse of thefrequency range.

An increase in the precision of the determination of the frequency maybe additionally achieved in accordance with a preferred embodiment ofthe invention under otherwise equal conditions by employing a circuit inwhich an additional impulse is generated which coincides with thetime-wise center of the gate impulse used, and is used in place of thecomparator impulse as the time marking point. As a result, even when thegate impulse length to acheive the greatest resolution exceeds theborderline value thereof, the attainable precision is greater than canbe accomplished with prior art circuits.

In accordance with another modification of the invention, comparatorimpulses produced during both forward and return variations in thewobble voltage are formed, each of which is operable to. trigger a gatepulse of predetermined, particularly adjustable, length which opens acounter gate circuit whereby the counting result is derived by the totalof impulses counted during the duration of each gate impulse, wherebythe end result is derived from the addition of the two impulsesubtotals. The respective gate impulses preferably are of equal durationand at least one of the comparator impulses is employed as the markabletime point.

In addition to the important advantage of the invention that thefrequency may be indicated digitally, as a result of the adjustabilityof the length of the gate impulse, the precision with which thefrequency determination may be made is freely selectable in accordancewith specific requirements.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings wherein like referencecharacters. indicate like or corresponding parts,

FIG. 1 illustrates the general circuit embodying th present invention,as utilized for measurement of frequency dependent transmissionproperties of a four terminal network; I

FIG. 2 illustrates in detail a preferred embodiment of a portionv of thecircuit of FIG. 1;

FIG. 3 represents a voltage time diagram at various points in the,circuit of FIGS. 1 and 2;

FIG. 4 illustrates in greater detail another preferred embodiment of aportion of the circuit of FIG. 1;

FIG. 5 represents voltage time diagrams, similar to FIG. 2, at variouspoints of the circuits of FIGS. 1 and 4; and

FIG. 6 broadly illustrates a circuit similar to FIG. 1

in which the frequencies of several markable time points may bemeasured.

DETAILED DESCRIPTION OF THE INVENTION The invention will initially begenerally discussed, primarily in connection with the disclosure of FIG.I, followed by a detailed description of two preferred embodiments ofthe invention, one illustrated in FIG. 2 and the other in FIG. 4 andlast, an arrangement for use in connection with a plurality of markingpoints within the frequency range, generally illustrated in FIG. 4.

GENERAL CONSTRUCTION Referring to FIG. 1, the reference numeral 1generally indicates a continuously frequency-modulated transmitter,particularly a wobbulatable transmitter, the frequency of whichisadapted to be varied by a frequency control voltage U, which isapplied to the control input 2 thereof, with such voltage being producedby a generator 3. The control voltage U. expediently has a time-linearcourse, more particularly a sawtooth or triangularly shaped course whichhas a periodic time dependency suitable for use as the control (wobble)voltage for the transmitter l. The voltage U, simultaneously is suppliedto a first input of a comparator 4 whose second input is connected to anadjustable DC voltage U,, the comparator 4 being operable to produce inthe presence of a predetermined amplitude relation, for example uponequality of amplitude, a comparator impulse 5 which is supplied to atriggerable inpulse-generating circuit 6. The circuit 6 is operative,upon the arrival of a comparator impulse 5, to produce a rectangularlyshaped gate impulse 7 which is supplied to the upper input of a gatecircuit 8, illustrated in the example of FIG. 1 as a NAND gate. The gate8 is adapted to be open for the duration of the impulse 7. The lowerinput of the gate 8 is operatively connected to the output of thetransmitter 1 whereby in the presence of the impulse 7, and opening ofthe gate 8, voltage impulses from the transmitter 1 and having a uniformpolarity of the AC voltage U, may pass to an impulse counter 9 whichwill therefore count the total number of impulses passing through thegate for the duration of the impulse 7. The impulse-generating circuit 6also delivers over a line 10 the comparator impulse 5, or, insteadthereof, another impulse 11, as hereinafter described, which in eachcase designates a point of time applicable to the frequency f oftransmitter l. The impulse-generating circuit 6 may also be providedwith an output 43 at which can be derived an evaluation signal U whichcauses suitable operation of the impulse counter, i.e., to indicate,store or record the counting result.

By additional circuitry, i.e., that appearing to the right of theterminals 12, 13 and 14, a measuring set is produced for use in themeasurement of the transmission properties, in dependency uponfrequency, of a four-terminal network X whose input is connected to theterminal 12. The output 15 of the four-terminal network is connected toan amplifier 16, followed by a rectifier 17 whose output voltage issupplied at 18 to one deflection system ofa visual or recordingapparatus 19, for example, an oscilloscope 20. Simultaneously therewiththe frequency control voltage U, is supplied to the other deflectionsystem of the oscilloscope 20 of the apparatus 19 over the terminal 21.

There thus results a pictorial presentation 22 as a function of thevarying frequency of the transmitter l with respect to the time base ofthe instrument 19, representing the course of the curve of the measuringvoltage appearing at the output 15 of the four-terminal network, thusrepresenting, for example, a measurement of the attenuation thereof. Theimpulse 5 and/or 11 is supplied to the frequency marking input 23 of theapparatus 19 and in known manner produces a frequency marking point, forexample, in the form of an additional deflection 24 of the electron beamin vertical direction or in the form of a brighter or a blackedout spotappearing at the selected point on the frequency curve.

An evaluation device or apparatus 25 may also be provided and connectedat its terminals 18 and 23' to the terminals 18 and 23 in lieu of theapparatus 19. Such a device may, for example, contain a gate circuit 26and a suitable evaluation structure 27, such as a digital voltmeter. Animpulse 5 and/or 11 in known manner produces a short duration opening ofthe gate circuit 26 whereby a reading or measurement value appearing atthe terminal 18' can be evaluated, preferably digitally. The possibilitythus exists, for example, to effect a comparison between the digitalreading value obtained in 27 with respect to the counting result of theimpulse counter 9, indicating the measurement frequency.

in accordance with one embodiment of the invention, the comparatorimpulse 5 is employed, if necessary, following suitable amplificationand/or pulse formation, to directly mark the point of time. Theprecision of the frequency determination thereby depends primarily onthe length of the gate impulse 7, which may be termed the counting time1,. Assuming that the frequency of the transmitter 1 changes during thecounting time from an initial value f, to the terminal value f linearlywith respect to time, the counting result is in error by the amount ofAf (f, f /2) (df/dt) (t,/2) in the event the precision of the systemillustrated is to be limited to substantially that achievable in priorart circuits, the error Af will not be greater than that resulting onthe following basis: if df:dt represents the variation of the frequencyin time, t represents the time for the passage of the frequency from oneend of its alternation to the other, r is the upper limit or threshholdvalue of the counting time still available, and m is the image screenresolution (for example, in percent of the screen width) of the viewinginstrument employed in the prior art circuits:

tw i nnur/ fma.t

There follows therefrom If no time linearity exists, I, corresponds inthe most unfavorable situation to the product 1,, m.

If the length of the gate impulse 7 is so selected that it is smallerthan the maximum permissible counting time t, the point of time markedby the impulse 5 may be determined within the frequency range, relativeto the counted transmission frequency f, with greater precision thanheretofore achieved in the prior art arrangements. By increasing theresolution of the impulse counter 9 by extending the counting time t, atsmall frequency ranges, it is possible that the above mentioned limitingvalue t, is exceeded. However, it is possible to achieve in such case anaccuracy greater than that of the circuits of the prior art byutilization of a further embodiment of the invention; and in particularby so designing the circuit 6 that an additional impulse 11 is providedwhich coincides, time-wise, with the center of the gate impulse 7 andthus may be substituted for the comparator impulse 5 so that Af moves ata time-linear frequency change toward 0, independently of the length ofthe counting time 1,.

THE CIRCUIT OF FIG. 2.

FIG. 2 illustrates in detail, a preferred embodiment of the triggerable,impulse generating means 6, fabricated from components employed inlogical circuit techniques. The comparator impulse 5 appearing at theoutput of the comparator 4 is supplied to the upper input of a NAND gate28 which is opened over its lower input during a frequency variationwhich moves from its lower threshhold value toward its upper threshholdvalue by a DC signal, and is closed during the return travel, i.e.,during the frequency variation from the upper toward the lowerthreshhold value. This situation may also be expressed by designatingthat the lower input of gate 28 has a signal value l thereat during theforward variation, and a signal value thereat during the return travel.In the circuit embodiment illustrated, the DC signal is derived from thefrequency control voltage U, over a differentiation stage 3a.

The output of the NAND gate 28 is connected to the upper input of a NANDgate 29 whose output is connected to the counting input 30 of a binarydivider stage 31, the outlet Q of which, following the arrival of anerasing impulse R, is in a 0 state. Such output 0 is connected to thelower input of a NAND gate 32and also to the input I of a JK flip-flopstage 33. The upper input of the gate 32 and the input C1 of theflip-flop stage 33 are connected to a source of normal frequencyimpulses U,,. Upon the arrival of an impulse at the input C1, thelogical condition at the input] is transferred to the output Q thereof,with the operating impulses thus being derived from the normal frequencyimpulses Q,,. The output Q of the stage 33 is connected with one (lower)input of the NAND gate 8 whose output is connected to the input of theimpulse counter 9 which preferably is decadic. The second (upper) inputof the gate 8 is supplied with the output voltage U, of the transmitter1 whose instantaneous frequency f, is to be determined at the point oftime marked by the comparator impulse or the impulse 11 within thevariable frequency range.

The output of the NAND gate 32 is connected to the input of anadditional, preferably decadic, counter 35 which counts the impulses ofthe normal frequency f,,, the respective counting outputs 37 of whichare individually selectable by means of the movable switch contact 36,the selected output being supplied to the input of a negation stage 38whose output is connected to the lower input of the NAND gate 29.

In accordance with the first circuit embodiment previously referred to,employing the comparator impulses 5 as the marking criterion, suchimpulses are supplied directly to the terminal 13 over the conductor andadditional connection 10', illustrated partially in broken lines. Itwill be appreciated that the connecting path 10 may, of course, includeimpulse-forming and- /or amplifying circuitry irrespective of whichthere may be considered a direct marking by the comparator impulse 5 ofthe point of time for which the frequency f, is to be determined.

In accordance with the second circuit embodiment previously referred to,wherein the direct marking of the point of time is determined by anadditional impulse II, the circuit connection 10 is eliminated and anadditional circuit is provided comprising a RC member 39, a NAND gate 40and a negation stage 41 whose circuit connections into the previouslydescribed circuitry is indicated in broken lines. In this arrangement,the output of the negation stage 38 is connected over the RC member 39with one input of the NAND gate 40 whose second input is connected tothe movable contact 36 and thus may be connected to a selected output 37of the counter 35. The output of the gate 40 is operatively connectedover the negation stage 41 and conductor 10 to the terminal 13.

The signal which may be considered a logical 1" during the forwardfrequency travel and to a logical 0 during the return travel, suppliedto the second input of the NAND gate 28 over the differentiation stage3a is also supplied to the input J of a JK flip-flop stage 42 whoseoutput Q is connected to the output terminal 43, operative to supply theevaluation signal U, to the counter 9. The logical state 0 (ground) thusexists at the input K of stage 42 while the input Cl thereof isconnected to the output Q of the stage 33.

The operation of the circuit illustrated in FIG. 2 will be explainedwith the aidof the voltage-time diagrams illustrated in FIG. 3, therespective lines 30 3f being coordinated as to time with respect to oneanother. FIG. 3a represents the normal frequency impulses U 3b thewobble voltage U, with a triangular time dependency and 3c depicts acomparator impulse occurring at time t, at which the voltage U, and theadjustable auxiliary voltage U, attain an equality of amplitude.

Referring to FIG. 2, the incoming comparator impulse 5 is conducted overthe NAND gate 28, as a negative impulse, to the upper of the gate 29during the forward frequency travel, i.e., during the ascending flank ofthe triangular voltage U,, as the lower input of the gate 28 has thesignal 1" thereat. As the signal I also appears at the lower input ofthe gate 29 in the rest position of the circuit, the production of apositive impulse results at the output of the NAND gate 29 whichapproximately corresponds to the comparator impulse 5. The positiveimpulse delivered by the gate 29 is supplied to the counting input 30 ofthe stage 31 whereby the output Q thereof, previously in restoredcondition of 0, is flipped to a 1. It will be appreciated that as longas a 1 appears at Q, the NAND gate 32 will remain open, permitting thenormal frequency impulse U, to pass into the impulse counter 35 andcounted therein, preferably decadically. When the counting results inthe counter 35 reaches that selected by the switch contact 36, an outputsignal U, (FIG. 3d) will be conducted over the contact 36 to thenegation stage 38 whereby the negative flank NF of the signal U, willresult in the generation of an additional counting inpulse appearing atthe output of the gate 29 and thus at the input 30 of the stage 31resulting in the output Q thereof being switched froma l to 0, theoutput 6 thereof simultaneously switching to a l The NAND gate 32therefore is blocked to the impulses U resulting in the conclusion ofthe counting operation in the counter 35.

During the counting operation in the counter 35, and in accordance withthe state of the output of the stage 31, a 1 is present at the input Jof the flip-flop stage 33 and a 0 is at the input K thereof.Consequently, the first negative flank of U,, (NFN of FIG. 3a) occurringafter the beginning of the counting of U, is supplied to the input C1 ofthe stage 33, as a result of which the l is shifted from J to Q, wherebythe NAND gate 8 is opened for the incoming oscillations of thetransmitter voltage U, whose frequency f, is to be determined, whichoscillations are thereby supplied to the impulse counter 9. Upontermination of the counting process in 35, resulting from a resetting ofthe stage 31, the 1" is removed from the input J of stage 33 andreplaced by a 0 so that upon the appearance of the first negative flankNFN' of the voltage U,,, following the end of a counting period, thecondition 0 appears at the output Q thereof. The gate 8 is therebyblocked with respect to the voltage U,,, concluding the countingoperation in the counter 9. The output voltage of stage 33, ilustratedin FIG. 3f which is present during a period of time as determined by theselected output of the counter 35 thus corresponds to the gate impulse 7of FIG. 1.

During the frequency return run, i.e., that corresponding to thenegative flank of the voltage Uf, no counting operation takes place inthe counters 35 and 9 as the NAND gate 28 is blocked as a result of thelogical signal O," and consequently the comparator impulses have noeffect. During the return run, it is expedient to derive from thevoltage U, a resetting inpulse R which is supplied to the individualstages of the counters 35 and 9 and the stages 31, 33 and 42. Inaccordance with the general circuit illustrated in FIG. 1, thecomparator impulses 5 may be transmitted over the connection illustratedpartially in broken lines, to the output conductor 10 and the terminal13, and thus is available for use in directly marking the time point t,associated with the frequency f to be determined.

In accordance with the second embodiment heretofore referred to, theconnection 10' is broken or eliminated and is replaced by the RC member39, gate 40 and negation stage 41. With this arrangement, the positiveflank PF of the output signal U is supplied to the upper input of thegate 40 and the lower input thereof is supplied through the RC member 39from the output of the negation stage 38, the RC member 39 beingdesigned with a suitable time constant as a result of which a l will bepresent at both inputs of the gate 40 for a predetermined period of timewhereby a positive impulse is delivered to the output 13, available as amarking impulse 11 at the time i.e., at the time-wise center of the gateimpulse 7 (FIG. 3e). Also, the negative flank NF of voltage U will notcause a delivery of an impulse at 13 as it is supplied to the one inputof gate 40 without delay and thus prior to and after its occurrence oneof the two inputs of gate 40 always must be disposed at 0.

The gate impulse 7 present at the output Q of stage 33 advantageously issupplied to the input C1 of a JK flip-flop stage 42 thereby causing,during the frequency forward run, the appearance of a l at the output Qthereof and thus to the terminal 43. It will be noted that in this case,the negative flank of 7 causes this action.

As a result, an evaluation signal U appears at the terminal 43, whichsignal initially occurs upon termination of the counting operations inthe counters 9 and 35 and continues to remain for the remainder of thefrequency forward run and at least a part of the frequency return run.Only with the arrival of a resetting impulse R, which expediently may bederived from the voltage U, during the frequency reverse run thereof,will the output of stage 42 be reset to 0" whereby the voltage U willdisappear at the output Q thereof.

The voltage U thus can be advantageously utilized to cause the counter 9to indicate or to emit the counting results, for example, by anillumination control of suitable indicator or counting tubes associatedwith the individual counter stages, or to cause a transfer of thecounting results to the counting stages of a memory operativelyfollowing the respective counting stages.

It will be appreciated that by the utilization of the method ofdetermining the time base of the counter 9 by means of a second counter35 which counts the pulses of a normal frequency, the maximum errorthereby created is one duration of a period of the voltage U, and itwill be apparent that this can be maintained quite small by asufficiently high value for the frequency f,,. While an additional errorF results from the association of the counted frequency F, with the marktime point resulting from the fact that the counting operation does notimmediately start with the presence of the comparator impulse 5, butonly with the immediately following negative flank NFN of the voltage Ueven this error or imprecision may be restricted to a low value by acorrespondingly high value of the frequency f,,. For example, a normalfrequency f,, of one M or higher, may be employed, whereby F is at themost one microsecond. However, when marking is effected at the timepoint t: by means of the impulse II, the error F is eliminated.

THE CIRCUIT OF FIG. 4

FIG. 4 illustrates a further preferred embodiment of the invention, withFIG. 4 generally corresponding to the circuit of FIG. 2 and thusinsertable in the circuit of FIG. 1, and with FIG. 5 generallycorresponding to FIG. 3 and illustrating representative voltages atvarious points of the circuit. This construction operationally is quitesimilar to that heretofore described, this embodiment however employingboth the forward and the return run of the frequency variations of thevoltage U, whereby comparator pulses are produced for both the ascendingflank and the descending flank of the voltage U, to produce two gateimpulses 7a (ascending) and/or 7d (descending) which preferably are ofequal duration. In this case the impulse counter 9 is adapted to counttwo impulse sub-totals which are added and the grant total of both isthen evaluated as a counting result. Likewise, in this arrangement, atleast one of the comparator impulses 5, if necessary or desirablefollowing corresponding amplification and/or pulse formation, isconducted over the conductor 10 of FIG. 1 for marking the time point ofthe frequency f, of the transmitter 1 to which the counting result ofthe impulse counter 9 is associated.

Referring to FIG. 4, the comparator impulse 5, delivered by thecomparator 4 is supplied to the upper input of the gate 29 which in thisembodiment is an OR gate, whose output is connected to the input 30 ofthe binary divider stage 31. The output Q of the stage 31, whichfollowing the arrival of a resetting impulse is in a 0" state, isconnected to the lower input of the N AND gate 32, to the upper input ofwhich is connected the source of normal frequency impulses UN having thefrequency f,,, and also to the input J of the JK flip-flop stage 33,which upon the arrival of an impulse at the input C1 operativelyswitches the logical data state appearing at the input J to the outputQ. The output 6 of the stage 31 is connected to the input K of the stage33.

It will be apparent that the controlling impulses for the stage 33, asin the arrangement of FIG. 2, are derived from the normal frequencyimpulses U,,. The output 0 of stage 33 is connected to the lower inputof the NAND gate 8 whose output again is connected to the input of thepreferably decadic impulse counter 9. The upper input gate 8 isconnected to receive the output voltage U, of the transmitter 1 whoseinstantaneous frequency f, is to be determined at the point of timemarked by the comparator impulse 5 within the frequency range. Theoutput of the NAND gate 32 is connected to the input of an additional,likewise preferably decadic counter 35 which again counts the impulsesof the normal frequency U,,. As in the previous circuit of FIG. 2, anyone of the outputs 37 of the respective counter stages may, by means ofthe movable switch 9 contact 36, be operatively connected to the lowerinput of the OR gate 29.

A J K flip-flop stage 42 is additionally provided, at the input J ofwhich appears a logic 1" during the frequency forward run and a duringthe frequency return run, as a result of the connection of such inputover the conductor 44 to the output of the differentiation stage 3a, theinput of which is connected to the frequency control voltage U,. As inthe circuit illustrated in FIG. 2, the input K of the stage 42 isconnected to ground while the input C1 is connected to the output 0 ofstage 33. The output 0 of the stage 42 is connected to the upper inputof a NAND gate 45, the lower input of which is connected to the output Qof the stage 33. The output of the gate 45 is connected over a negationstage 46 to the input C1 of an additional JK flip-flop stage 47 whoseinput 1 is connected over a negation stage 48 and conductor 44 to theoutput of the differentiation stage 3a, while the input K of the stage47 is grounded. The output Q of stage 47 is connected to the terminal 43at which the evaluation signal U, appears and may be operativelyconnected to the counter 9.

The manner of operation of the embodiment illustrated in FIG. 4 will bereadily apparent when considered with the voltage-time diagramsillustrated in FIG. 5, in which FIG. 5a represents the normal frequencyimpulses f,,, and FIG. 3b illustrates the frequency control voltage U,having a triangular time dependency and its association with theadjustable auxiliary voltage U,.

As in the circuit of FIG. 2, upon amplitude equality of voltages U, andU,, at the time a comparator impulse 5 (FIG. 5c) occurs which isconducted over the OR gate 29 to the counting input of the binarydivider stage 31, as a result of which a l appears at the output 0thereof, while the complementary output 0 changes from 1 to 0." As longas a 1" is present at the output Q of the stage 31, the NAND gate 32will remain open for normal frequency impulses U, (FIG. 5a) which thusmay pass into the impulse counter 35 where they are suitably counted,preferably decadically. Again, when a total is reached in the counter,as determined by the selection of the desired counter output 37 inaccordance with the position of the movable switch contact 36, an outputsignal U, is obtained whose positive flank Pf is supplied over the gate29 to the input 30 of the stage 31 as an additional counting impulse. Asa result, the output 0 of stage 31 is returned from a l to a 0 while Qreturns to a l. The NAND gate 32 is thereby blocked with respect to thenormal frequency U and the counting operation in the counter 35 is thusconcluded.

With the initiation of the counting operation in the counter 35, inaccordance with the output conditions of the stage 31, a l appears atthe input J of the JK flip-flop stage 33 while a 0" appears at the inputK. Consequently, the immediately following negative flank of the voltageU, (NFN in FIG. 5a) which is supplied to the input C1 of stage 33results in the 1 being switched from the input J to the output Q andthus supplied to the lower input of the NAND gate 8, opening the latterfor incoming oscillations of the transmitter voltage U,, which are thuscounted in the counter 9. Upon termination of the counting operation inthe counter 35, resulting from the resetting of stage 31, the ldisappears from the input J of stage 33 and is re- '10 placed by 0 sothat upon the appearance of the immediately following negative flank ofthe voltage U, the output 0 returns to a 0 stage. The output voltage ofstage 33, illustrated in FIG. 5d, as determined by the selected output37, thus corresponds to the gate impulse 7 of FIG. 1. v I

It will be apparent that during the frequency forward run, that isduring the ascending flank of the voltage U,, a logic l is present atthe input J of stage 42 while at the same time the logic 0" is conductedover the negation stage 48 to the input J of stage 47. If a gate impulse7 now appears at the output of stage 33, its negative flank is utilizedover the input C1 of stage 42 to effect a transfer of the l from input Jto output Q. The NAND gate 45 will thereby have a logic 1 at its upperinput and. as the gate impulse 7 simultaneously is conducted to thelower input of such gate its lower input will thereby be switched to 0"so that a l remains unchanged at the output of gate 45. Thus, as aresult of the negation stage 46, a 0 is conducted to and appears at theinput C1 of the stage 47. Consequently, during the forward run no signalU occurs at the terminal 42 which could be supplied to the counter 9 asan evaluation signal and the counter thus does not indicate the partialresult formed during the frequency forward run.

During the frequency return run the process of the counting of theimpulses of the voltage U are repeated in the manner described wherebythe initiation of the counting operation is determined by the comparatorimpulse 5' (FIG. 5e) which is produced upon amplitude equality of thevoltages U, and U Following the start of the counting operation incounter 35 the immediately following negative flank of U,,, designatedin FIG. 5a as NFN', causes the transfer of the l appearing at J of stage33 to the output Q thereof whereby an additional gate impulse 7d (FIG.5f) is formed whose length depends in like manner to that of the impulse7a on the position of the movable switch contact 36. If no change hastaken place in the setting thereof, the forward and return run gateimpulses 7a and 7d are of equal duration.

The rear flank of the impulse 7d supplied to the input C1 of stage 42results in the transfer of the logic 0 from the input J of stage 42 tothe output Q thereof whereby both inputs of the gate circuit 38 arechanged at this instant from the state 1 to the state 0, resulting in aswitching at the output side thereof from O to 1. Negation 39 effects aninversion thereof whereby the negative impulse flank resulting at theinput C1 of stage 47 results in the transferring of the logic 1, presentat J during the frequency return run, to the output 0, thereby supplyingan evaluation signal U to the terminal 43 and thus to the counter 9.

The signal U, thereby causes the counter 9 to indicate or emit thecounting result, for example by an illumination control of suitableindicator tubes associated with the individual counter stages or bytransferring the counting result to a subsequently connected memory 9a(FIG. 4). The use of a memory in the wobble operation has the advantagethat even with the marking of a point shortly after the beginning of thefrequency transmission there will not be unduly large intervals betweenthe individual indications of the counting results, whereas in theabsence of such a memory the illumination control, particularly at lowwobble frequencies, could produce an undesired flickering.

Upon termination of the complete counting operation, as determined bythe evaluation signal U,,, a resetting impulse is derived, preferablyfrom a suitable voltage, for example the voltage U,, fed from thecircuit 6 of FIG. 1, such resetting impulse being supplied to therespective counter stages of the counters 9 and 35 and the stages 31,33, 42 and 47, thereby resetting them into their rest position, andpreparing the circuit for the immediately following counting operation.

It will be appreciated that in this embodiment, employing a secondcounter 35 in which the normal frequency f,, is counted, for each of thetwo time bases 7a and 7d for counter 9, the resulting error amounts ineach case to not more than one period duration of the voltage u,,.Likewise, by adding the two sub-totals obtained during the forward andreverse runs, and assuming gate impulses 7a and 7d of equal duration, aswell as a constant frequency variation rate of voltage U,,, anadditional error occurs for the forward and reverse runs in theassociation of the counting result of 9 to the point of time designatedby or 5' which corresponds at most to half a period duration of voltageU,,. This error may be attributed to the fact that the time distance ofthe impulse 5 at the beginning of the gate impulse 7 may vary at themost by one period duration of voltage U,,. The maximum error withrespect to the association of the counted frequency to the marked timepoint under these conditions thus amounts to half a period duration ofvoltage U,, as a result of the differential duration of the time bases,and in addition, to another half period of time as a result of thementioned differential time distances. As in the previous arrangement,such errors can be kept at a suitably small figure by the employment ofa sufficiently high frequency for the voltage f,,, for example 1 MC.

THE CIRCUIT OF FIG. 6

FIG. 6 illustrates the utilization of the present invention to provide aplurality of different marker points, each at its own point of time forexample within a single passage of the frequency from its own limitingvalue to its other limiting value. In this arrangement, a separatecomparator 4, 4' and 4" is provided for each time point, each beingcontrolled by its respective adjustable auxiliary voltage U,, U1, andU1", whereby respective comparator impulses 5, 5 and 5" are producedwhich are staggered in time and conducted to suitable impulse-generatingmeans 6 to produce respective corresponding gate impulses 7, 7 and 7",likewise staggered in time. The gate pulses are supplied to the gatecircuit 8 and the counting results obtained during the presence of eachgate impulse are suitably conducted from the counter 9 and stored inindividual memories 9a, 9b and 9c.

It will be appreciated that the example illustrated in FIG. 6 is merelyillustrative to explain the principle and is not limited to merely threemarkable time points during one frequency passage. Likewise, anymultiplicity of time points may be similarly utilized and the frequencyvalues f, thereof determined, providing the time duration of thecomparator impuses is greater than the preselected counting time.

Having thus described my invention, it will be obvious to those skilledin the art from the disclosure herein given that various immaterialmodifications may be made in the same without departing from the spiritof my invention.

I claim as my invention:

1. A circuit for determining the frequency associated with a time pointdefined by the occurrence of a marking impulse during the frequencysweep of a signal produced by a wobble fre uency transmitter employingan adjustable auxiliary wobble control voltage produced by a generatorand controlling the frequency in function of time, comprising acomparator arranged to effect an amplitude comparison between a presetvoltage supplied to one input of said comparator and said auxiliarycontrol voltage supplied to a second input of said comparator, operativeto produce a comparator impulse upon a predetermined comparative result,which forms a marking impulse, the occurrence of which defines said timepoint, an impulse counter for counting halt wave impulses emanating fromthe frequency swept signal and a control circuit responsive to suchcomparator impulses, operatively connecting said transmitter and counterfor controlling the admission of the the said emanating impulses to saidcounter, to effect a counting therein of said associated frequency.

2. A circuit according to claim 1, for effecting the determination ofthe respective frequencies of a plurality of such time points defined bythe occurrence of a plurality of marking impulses within onepredetermined run over the frequency sweep range, comprising acomparator for each such time point, each of which is supplied with saidauxiliary wobble voltage and with a respective different preset voltage,for respective comparisons with said auxiliary voltage, and storagemeans operatively connected to said counter for individual consecutivestorage of the respective counting results for each of such definabletime points.

3. A circuit according to claim 1, wherein said control circuit isconstructed to effect entry of said emanating pulses into said counteronly during the forward part of the frequency sweep, with the totalthereby derived in said counter comprising the counting total.

4. A circuit according to claim 1, wherein said control circuit isconstructed to effect entry of said emanating pulses into said counterduring both forward and return parts of the frequency sweep with the sumof the totals derived during the forward part and the immediatelyfollowing return part comprising the counting tota].

5. A circuit according to claim 1, for the frequency dependentmeasurement of the transmission properties of a four terminal network,comprising in further combination a digital voltage evaluation device, agate circuit having its output connected to the input of said digitalevaluation device, the frequency swept signal of said transmitter beingsupplied to the imput of said four terminal network, the output of saidfour terminal network being connected to one input of said gate circuit,the controlling input of said gate circuit having comparator pulsessupplied thereto.

6. A circuit according to claim 1 for the frequencydependent measurementof the transmission properties of a four terminal network, furthercomprising an indicating device, said frequency swept signal of saidtransmitter being supplied to the input of said four terminal network,and the output thereof connected to said indicating device, said wobblevoltage being supplied to said device and operable to maintain adeterminable time base, said comparator impulse being conducted to saidindicating device as a marking pulse.

7. A circuit according to claim 1, comprising in further combinationmeans connected to said control circuit for creating a center impulsewhich is present at the time-wise center of the admission time of saidemanating impulses to said counter and thus usable in lieu of thecomparator impulse for defining the said time point.

8. A circuit according to claim 7, for the frequencydependentmeasurement of the transmission properties of a four terminal network,comprising in further combination a digital voltage evaluation device, agate circuit having its output connected to the input of said digitalevaluation device, the frequency swept signal of said transmitter beingsupplied to the input of said four terminal network, the output of saidfour terminal network being connected to one input of said gate circuitand another input of said gate circuit having said center pulsessupplied thereto.

9. A circuit according to claim 7 for the frequencydependent measurementof the transmission properties of a four terminal network, furthercomprising an indicating device, said frequency swept signal of saidtransmitter being supplied to the input of said four terminal network,and the output thereof connected to said indicating device, said wobblevoltage being supplied to said device and operable to maintain adeterminable time base, said center impulse being conducted to saidindicating device as a marking pulse.

10. A circuit according to claim 1, wherein said control means comprisesimpulse generating means and a gate circuit operatively connecting saidtransmitter and counter, said impulse generating means being connectedto said gate circuit and operative to deliver thereto in response to acomparator impulse, a gate impulse of predetermined length, during whichsuch gate is open for the passage of impulses from said transmitter tosaid counter.

11. A circuit according to claim 10, wherein said impulse generatingmeans comprises a second gate circuit to which said comparator pulsesare supplied, and a second counter operatively connected thereto, asource of standard frequency impulses operatively connected by saidsecond gate circuit to said second counter, the latter being operativeto deliver a retangular voltage, the frequency of which is asub-multiple of said standard frequency, so that a blocking of saidsecond gate circuit occurs in the presence of the flank at the end of aperiod of said rectangular voltage, whereby the gate impulse for saidfirst gate may be derived from a signal defining the open duration ofthe second gate circuit.

12. A circuit according to claim 11, wherein said impulse generatingmeans further includes a binary divider stage to which comparatorimpulses are supplied, means for deriving an impulse from saidrectangular voltage flank and means for supplying said last mentionedimpulse to said divider stage for blocking the same whereby the outputof said divider stage is operative to supply the gate impulse for saidsecond gate.

13. A circuit according to claim 12, wherein said impulse generatingmeans further includes a JK flip-flop stage having its clock inputsupplied by said source of standard frequency impulses, the output ofsaid divider stage being connected to another input of said flip-flopstage and the output thereof being connected to said first gate wherebyswitching of the latter occurs in each case in the presence of theimmediately following flank 14 of predetermined polarity of saidstandard frequency impulses.

14. A circuit'according to claim 13, comprising in further combination,means responsive to said rectangular voltage for creating from a flankthereof present at the center of the period of said rectangular voltage,a center impulse which thus is present at the center of the gate impulsefor said first gate and usable for defining the said time point.

15. A circuit according to claim 14, wherein said center pulse formingmeans comprises a NAND gate, to one input of which said rectangularvoltage is supplied, and a delay member and a negation stage seriallyconnected, and operatively conducting said rectangular voltage toanother input of said NAND gate, said center pulse being obtained at theoutput of said NAND gate.

16. A circuit according to claim 15, wherein said impulse generatingmeans further includes a second JK flip-flop stage, the clock input ofwhich is supplied with said gate impulses for the first gate and anotherinput is supplied with a signal derived from said wobble control voltagewhereby said signal is dependent upon the part (forward or return) ofthe frequency sweep of said transmitter, the output of said secondflip-flop stage being operable to supply an evaluation signal forevaluating the count of said first counter.

17. A circuit according to claim 16, wherein said second flip-flop stageincludes means for producing an evaluation signal at the end of eachgate impulse for said first gate, whereby the evaluated total in saidfirst counter represents the total of the counting operation during asingle gate impulse.

18. A circuit according to claim 16, comprising in further combination,means operatively connecting the" output of said second flip-flop stageand said first counter for conducting such an evaluation to said firstcounter only at the end of a gate impulse for said first gate occurringduring return part of the frequency sweep, whereby the total evaluatedin said first counter represents the sum of the totals counted incounting op erations during two of such gate pulses respectivelyoccurring during a forward part and an immediately following return partof the frequency sweep.

19. A circuit according to claim 18, wherein said means connecting saidsecond flip-flop stage and said first counter comprises a thirdflip-flop stage, the output of which is connected to said first counterfor supplying an evaluation pulse thereto, a gate having its outputconnected by a negation stage to the clock input of said third flip-flopstage, one input of said lastmentioned gate being connected to theoutput of said second flip-flop state and another input conneced toreceive gate impulses for said first gate, said third flipflop stagehaving another input connected by a negation stage to the means supplysaid signal, dependent upon the part (forward or return) of thefrequency sweep derived from said wobble control voltage.

20. A circuit according to claim 19, wherein said means for supplyingsaid blocking impulse to said divider state comprises a gate, the outputof which is connected to the input of said divider stage, one input ofsaid last-mentioned gate being connected over a negation stage to theoperative output of said second counter, another input of saidlast-mentioned gate being connected to the output of a further gate,said further gate having two imputs, one of which is con- 16 shapingsaid comparator impulses, to the input of which said comparator impulsesare conducted, the output of said impulse generator circuit beingoperatively connected to said counter.

l l i k

1. A circuit for determining the frequency associated with a time pointdefined by the occurrence of a marking impulse during the frequencysweep of a signal produced by a wobble frequency transmitter employingan adjustable auxiliary wobble control voltage produced by a generatorand controlling the frequency in function of time, comprising acomparator arranged to effect an amplitude comparison between a presetvoltage supplied to one input of said comparator and said auxiliarycontrol voltage supplied to a second input of said comparator, operativeto produce a comparator impulse upon a predetermined comparative result,which forms a marking impulse, the occurrence of which defines said timepoint, an impulse counter for counting halfwave impulses emanating fromthe frequency swept signal and a control circuit responsive to suchcomparator impulses, operatively connecting said transmitter and counterfor controlling the admission of the the said emanating impulses to saidcounter, to effect a counting therein of said associated frequency.
 2. Acircuit according to claim 1, for effecting the determination of therespective frequencies of a plurality of such time points defined by theoccurrence of a plurality of marking impulses within one predeterminedrun over the frequency sweep range, comprising a comparator for eachsuch time point, each of which is supplied with said auxiliary wobblevoltage and with a respective different preset voltage, for respectivecomparisons with said auxiliary voltage, and storage means operativelyconnected to said counter for individual consecutive storage of therespective counting results for each of such definable time points.
 3. Acircuit according to claim 1, wherein said control circuit isconstructed to effect entry of said emanating pulses into said counteronly during the forward part of the frequency sweep, with the totalthereby derived in said counter comprising the counting total.
 4. Acircuit according to claim 1, wherein said control circuit isconstructed to effect entry of said emanating pulses into said counterduring both forward and return parts of the frequency sweep with the sumof the totals derived during the forward part and the immediatelyfollowing return part comprising the counting total.
 5. A circuitaccording to claim 1, for the frequency dependent measurement of thetransmission properties of a four terminal network, comprising infurther combination a digital voltage evaluation device, a gate circuithaving its output connected to the input of said digital evaluationdevice, the frequency swept signal of said transmitteR being supplied tothe imput of said four terminal network, the output of said fourterminal network being connected to one input of said gate circuit, thecontrolling input of said gate circuit having comparator pulses suppliedthereto.
 6. A circuit according to claim 1 for the frequency-dependentmeasurement of the transmission properties of a four terminal network,further comprising an indicating device, said frequency swept signal ofsaid transmitter being supplied to the input of said four terminalnetwork, and the output thereof connected to said indicating device,said wobble voltage being supplied to said device and operable tomaintain a determinable time base, said comparator impulse beingconducted to said indicating device as a marking pulse.
 7. A circuitaccording to claim 1, comprising in further combination means connectedto said control circuit for creating a center impulse which is presentat the time-wise center of the admission time of said emanating impulsesto said counter and thus usable in lieu of the comparator impulse fordefining the said time point.
 8. A circuit according to claim 7, for thefrequency-dependent measurement of the transmission properties of a fourterminal network, comprising in further combination a digital voltageevaluation device, a gate circuit having its output connected to theinput of said digital evaluation device, the frequency swept signal ofsaid transmitter being supplied to the input of said four terminalnetwork, the output of said four terminal network being connected to oneinput of said gate circuit and another input of said gate circuit havingsaid center pulses supplied thereto.
 9. A circuit according to claim 7for the frequency-dependent measurement of the transmission propertiesof a four terminal network, further comprising an indicating device,said frequency swept signal of said transmitter being supplied to theinput of said four terminal network, and the output thereof connected tosaid indicating device, said wobble voltage being supplied to saiddevice and operable to maintain a determinable time base, said centerimpulse being conducted to said indicating device as a marking pulse.10. A circuit according to claim 1, wherein said control means comprisesimpulse generating means and a gate circuit operatively connecting saidtransmitter and counter, said impulse generating means being connectedto said gate circuit and operative to deliver thereto in response to acomparator impulse, a gate impulse of predetermined length, during whichsuch gate is open for the passage of impulses from said transmitter tosaid counter.
 11. A circuit according to claim 10, wherein said impulsegenerating means comprises a second gate circuit to which saidcomparator pulses are supplied, and a second counter operativelyconnected thereto, a source of standard frequency impulses operativelyconnected by said second gate circuit to said second counter, the latterbeing operative to deliver a retangular voltage, the frequency of whichis a sub-multiple of said standard frequency, so that a blocking of saidsecond gate circuit occurs in the presence of the flank at the end of aperiod of said rectangular voltage, whereby the gate impulse for saidfirst gate may be derived from a signal defining the open duration ofthe second gate circuit.
 12. A circuit according to claim 11, whereinsaid impulse generating means further includes a binary divider stage towhich comparator impulses are supplied, means for deriving an impulsefrom said rectangular voltage flank and means for supplying said lastmentioned impulse to said divider stage for blocking the same wherebythe output of said divider stage is operative to supply the gate impulsefor said second gate.
 13. A circuit according to claim 12, wherein saidimpulse generating means further includes a JK flip-flop stage havingits clock input supplied by said source of standard frequency impulses,the output of said divider stage being connected to another inPut ofsaid flip-flop stage and the output thereof being connected to saidfirst gate whereby switching of the latter occurs in each case in thepresence of the immediately following flank of predetermined polarity ofsaid standard frequency impulses.
 14. A circuit according to claim 13,comprising in further combination, means responsive to said rectangularvoltage for creating from a flank thereof present at the center of theperiod of said rectangular voltage, a center impulse which thus ispresent at the center of the gate impulse for said first gate and usablefor defining the said time point.
 15. A circuit according to claim 14,wherein said center pulse forming means comprises a NAND gate, to oneinput of which said rectangular voltage is supplied, and a delay memberand a negation stage serially connected, and operatively conducting saidrectangular voltage to another input of said NAND gate, said centerpulse being obtained at the output of said NAND gate.
 16. A circuitaccording to claim 15, wherein said impulse generating means furtherincludes a second JK flip-flop stage, the clock input of which issupplied with said gate impulses for the first gate and another input issupplied with a signal derived from said wobble control voltage wherebysaid signal is dependent upon the part (forward or return) of thefrequency sweep of said transmitter, the output of said second flip-flopstage being operable to supply an evaluation signal for evaluating thecount of said first counter.
 17. A circuit according to claim 16,wherein said second flip-flop stage includes means for producing anevaluation signal at the end of each gate impulse for said first gate,whereby the evaluated total in said first counter represents the totalof the counting operation during a single gate impulse.
 18. A circuitaccording to claim 16, comprising in further combination, meansoperatively connecting the output of said second flip-flop stage andsaid first counter for conducting such an evaluation to said firstcounter only at the end of a gate impulse for said first gate occurringduring return part of the frequency sweep, whereby the total evaluatedin said first counter represents the sum of the totals counted incounting operations during two of such gate pulses respectivelyoccurring during a forward part and an immediately following return partof the frequency sweep.
 19. A circuit according to claim 18, whereinsaid means connecting said second flip-flop stage and said first countercomprises a third flip-flop stage, the output of which is connected tosaid first counter for supplying an evaluation pulse thereto, a gatehaving its output connected by a negation stage to the clock input ofsaid third flip-flop stage, one input of said last-mentioned gate beingconnected to the output of said second flip-flop state and another inputconneced to receive gate impulses for said first gate, said thirdflip-flop stage having another input connected by a negation stage tothe means supply said signal, dependent upon the part (forward orreturn) of the frequency sweep derived from said wobble control voltage.20. A circuit according to claim 19, wherein said means for supplyingsaid blocking impulse to said divider state comprises a gate, the outputof which is connected to the input of said divider stage, one input ofsaid last-mentioned gate being connected over a negation stage to theoperative output of said second counter, another input of saidlast-mentioned gate being connected to the output of a further gate,said further gate having two imputs, one of which is connected toreceive said comparator impulses, and the other input is connected tothe means supplying said signal dependent upon the part of the frequencysweep of said transmitter.
 21. A circuit according to claim 1,comprising in further combination, an impulse-generating circuit, forreshaping said comparator impulses, to the input of which saidcomparator impulses are conducted, the output of said iMpulse generatorcircuit being operatively connected to said counter.